Memory modules can include system components that attach to a memory bus. A memory module ubiquitous to most modern computer systems is the dual in-line memory module (DIMM). A conventional DIMM is populated with dynamic random access memory (DRAM) integrated circuits devices, for rapid access by a host through the use of a memory controller, and relatively low power consumption.
The need to preserve system RAM data has given rise to “image” type non-volatile DIMMs (NVDIMMs). A conventional image type NVDIMM is shown in FIG. 21. FIG. 21 shows one version of an NVDIMM according to the NVDIMM-N standard (JESD248) promulgated by JEDEC. A conventional NVDIMM 2101 can include DRAM 2103, as in a conventional DIMM, but can further include a controller 2105, NAND type flash memory 2107, and buffers 2109. The NVDIMM 2101 can include DIMM compatible connectors 2111 and can communicate via a CAS-RAS interface/protocol 2113. In standard operations, the DRAM of the NVDIMM can be accessed like a conventional DIMM. However, in response to certain system events (e.g., power loss, reset, or special command), the data stored in the DRAM can be written into the NAND storage (e.g., SAVE). Conversely, in response to other system events (e.g., power-on, reset, or other special command), the data stored in the NAND memory can be transferred back into the DRAM. Such data can then be accessible by a host, through access to the DRAM 2103.
While an image type NVDIMM, like that of FIG. 21, can provide a valuable feature to systems, such an architecture may be less suitable for other applications. For example, there is a desire to place even larger amounts of nonvolatile storage on memory modules. However, mirroring such large data amounts with DRAM would be extremely impractical. Accordingly, there is a desire to place very large, block-mode accessed nonvolatile memories onto the high-speed, multi-byte-wide, byte-addressable memory channel. The conventional approach to implement this is to provide a large controller which then steers all of the wide memory channel data to one or more nonvolatile memory channels.
FIG. 22 shows one proposed version of an NVDIMM according to a standard developed by JEDEC (NVDIMM-F standard). The NVDIMM 2201 does not include DRAM, and instead employs a larger controller 2205 with NAND 2207 storage. Being DIMM compatible, proposed NVDIMM 2201 also includes DIMM type connectors 2211 and can communicate via a CAS-RAS interface/protocol 2213. A drawback to such an approach can be the difference between bus access speeds and NAND access speeds, particularly during sustained accesses. As bus access speeds (e.g., DRAM speeds) outstrip NAND access speeds, large transfers between the NAND and controller can become a bottleneck. Another drawback can be the complexity and expense of implementing such a large controller device. Further, signaling at the interface of the controller can involve massive input/output (I/O) switching, which may be difficult to source or sink by a single integrated circuit.
FIG. 23 shows another version of an NVDIMM according to a standard currently under development by JEDEC (proposed NVDIMM-P standard). The proposed NVDIMM 2301 includes DRAM 2303 and NAND 2307 accessible by a large controller 2305. Proposed NVDIMM 2301 also includes DIMM compatible connectors 2311 and communicates via a CAS-RAS interface/protocol 2313. A drawback to an approach like that of FIG. 23 can include those noted above for the example of FIG. 22. In addition, proposed NVDIMM 2301 can have the added cost of including DRAM, as compared to FIG. 22. Further, proposed NVDIMM 2301 presents a significant signal routing challenge, particularly for data buses, which must be routed to/from the bus 2313 to the controller 2305, as well as from the controller 2305 to the DRAM 2303.